8255 / 82C55 PPI

Pinout

<->  PA3 1   8255   40 PA4 <->
<-> PA2 2 39 PA5 <->
<-> PA1 3 38 PA6 <->
<-> PA0 4 37 PA7 <->
--> !RD 5 36 !WR <--
--> !CS 6 35 RESET <--
--- GND 7 34 D0 <->
--> A1 8 33 D1 <->
--> A0 9 32 D2 <->
<-> PC7 10 31 D3 <->
<-> PC6 11 30 D4 <->
<-> PC5 12 29 D5 <->
<-> PC4 13 28 D6 <->
<-> PC0 14 27 D7 <->
<-> PC1 15 26 VCC ---
<-> PC2 16 25 PB7 <->
<-> PC3 17 24 PB6 <->
<-> PB0 18 23 PB5 <->
<-> PB1 19 22 PB4 <->
<-> PB2 20 21 PB3 <->

Software structure

struct PPI	=	// a standard 8255 chip
{
	byte	PORTA;	// Port A
	byte	PORTB;	// Port B
	byte	PORTC;	// Port C
	byte	CTRL; 	//
};

Hardware structure

Approximate VHDL entity only!

entity PPI_8255 is	-- 
port(
	rst:	in	std_logic;	-- Reset, active high
	n_cs: 	in	std_logic;
	n_rd:	in	std_logic;	-- Not Read 
	n_wr:	in	std_logic;	-- Not Write
	ph2:	in	std_logic;	-- CPU clock phase 2
	cs1:	in	std_logic;
	a: 	in	std_logic_vector(1 downto 0);

	d:	inout	std_logic_vector(7 downto 0);
	pa:	inout	std_logic_vector(7 downto 0);	-- Port A
	pb:	inout	std_logic_vector(7 downto 0);	-- Port B
	pc:	inout	std_logic_vector(7 downto 0);	-- Port C 
	);
end entity PPI_8255;

Revision history

2003-11-06 Pins 26 and 36 were swapped, PC0-3 were wrong way round. Thanks to Ryan B. for spotting this.