Acorn Atom in FPGA (Timing details)

Everything runs off a single crystal at the moment, at four times either the NTSC or the PAL colour carrier frequencies.

This is useful because there is a single master clock for the system, and it can easily generate the colour carrier.
In practice, the colour carrier is not required if sending RGB signals.

I also note that the NTSC crystals are more widely available, and are often used elsewhere. For example, smart card readers usually use a 3.58 MHz clock, and I have seen DTMF encoders/decoders use it too. Therefore it might be more useful to use an NTSC crystal for both TV systems, and have a second crystal for the least-likely scenario of a PAL TV without RGB input.

For now, the design copes with both types of crystal.

Designed timing

Parameter NTSC PAL Units    
Rational Decimal Rational Decimal
Fcarrier 4.5*35/44
= 315/88		 3,579,545.45
+/- 10		 17734475/4 4,433,618.75
+/- 5 		Hz   Colour carrier definition
Fcrystal 315/22 4 * fc =
14.318...		 17734475 4 * fc =
17.734475		 MHz   Master crystal
Fclk 315/11 Fcrystal * 2 =
28.63...		 3546895 Fcrystal * 2 =
35.46895		 MHz rate FPGA clock
Tclk 11/315 34.920634   28.193673 ns period
Divisor   2   5      
Fpixel = Fclk / Divisor = 315/44 7.159090909 7093790 7.09379 MHz rate Pixel
Tpixel 44/315 0.13968254   0.140968368 us  
Fmem = Fpixel / 2 = 315/88 3.579545455 3546895 3.546895 MHz rate Memory cycle
Tmem 88/315 0.279365079 1/3546895 0.281936736 us period
Fcpu = Fmem/2 = 315/176 1.789772727 17734475 1.7734475 MHz rate CPU cycle
Tcpu 315/352 0.558730159 1/17734475 0.563873472 us period
Tline = Tmem*228 20064/315 63.695... 228/3546895 64.281... us    
Tfield = Tline*262
(or 312 for PAL)		 5256768/315 16.688... 71136/3546895 20.0558... ms    
Tfield * 60
(or 50 for PAL)		 315406080
315000000		 1.001289142... 3556800/3546895 1.002792... s    
Frame rate = 1/Tfield 315/5256768 60.390779... 3546895/71136 49.860... Hz    

The above timings show that each cpu cycle contains four pixels.
Each cpu cycle contains ten clock pulses for the
One CPU cycle = two memory cycles = twenty (PAL) or 16 (NTSC) clock cycles
Recurring digits underlined.

6502 Timing

Symbol min typ max    
  0   0.050 ns PH0 to PH1 or PH2 edges
  10     ns Data hold time for reading
           

Other Timing

Symbol min typ max    
  0.229365079   0.249365079 ns memory cycle time less PH0 to PH1 or PH2 edges
           

Has to be PH2 to select multiplexer address.
PH0 is okay for the VDU, which latches RAM data on rising edge of PH0,
but not okay for the CPU, which latches RAM data on falling edge of PH2.
PH0 would turn off data too soon for CPU, so data hold time not satisfied.
PH2 is okay for CPU and also for VDU.

If memory is fast enough to present video data at rising edge of PH0,
should also be able to register cpu data at falling edge of PH0.

ROM Timing, internals to FPGA

Ideally this needs to be faster than the 28.193673 ns single clock period time.

Module Implementation Path from
rom_atom_kernel_hi   Port 'a_0' to Port 'd_0' : 25.320ns
rom_atom_kernel_lo block ram, 2K Clock 'clk' rising to Port 'd_0' : 10.829ns
Port 'oe' to Port 'd_0' : 9.140ns
rom_atom_utility   Port 'a_0' to Port 'd_0' : 14.387ns
rom_atom_basic block ram, 4K Clock 'clk' rising to Port 'd_0' : 11.636ns
Port 'oe' to Port 'd_0' : 9.140ns
pia8255_for_atom   Clock 'clk' falling to Port 'pia_d_0' : 9.102ns
Port 'a_0' to Port 'pia_d_0' : 10.209ns
via6522_for_atom   Clock 'clk' falling to Port 'via_d_0' : 9.437ns
Port 'en' to Port 'via_d_0' : 9.311ns
mapper   Port 'cpu_a_14' to Port 'sys_d_0' : 16.943ns

RAM Timing, 70 ns part

Read cycle Write cycle
Symbol min typ max  
tRC 70     Read cycle time
tAA -   70 Address access time
tCO -   70 Chip select to output
tOE -   35 Output enable to valid output
tLZ 10   - Chip select to low-Z output
tOLZ 5   - Output enable to low-Z output
tHZ 0   25 Chip disable to high-Z output
tOHZ 0   25 Output disable to high-Z output
tOH 10   - Output hold from address change
Symbol min typ max  
tWC 70   - Write cycle time
tCW 60   - Chip select to end of write
tAS 0   - Address set-up time
tAW 60   - Address valid to end of write
tWP 50   - Write pulse width
tWR 0   - Write recovery time
tWHZ 0   25 Write to output high-Z
tDW 30   - Data to write time overlap
tDH 0   - Data hold from write time
tOW 5   - End write to output low-Z

Key constraints:

An Alternative Timing with 27 MHz crystal

The International Telecommunications Union have a standard for video timing, based on a luminance sampling rate of 13.5 MHz.

Parameter NTSC PAL Units    
Rational Decimal Rational Decimal
Fclk   27   27 MHz   Master crystal
Divisor   4   4      
Fpixel = Fclk / Divisor = 27/4 6.75 27/4 6.25 MHz rate Pixel
Tpixel 4/27 0.148 4/27 0.140968368 us  
Fmem = Fpixel / 4 = 27/8 3.375 3546895 3.546895 MHz rate Memory cycle
Tmem 8/27 0.296 1/3546895 0.281936736 us period
Fcpu = Fmem / 8 = 27/16 1.6875 17734475 1.7734475 MHz rate CPU cycle
Tcpu 16/27 0.592 1/17734475 0.563873472 us period
Fline (27/2)/858 15734.265734 (27/2)/864 15.625 Hz    
Tline 858*2/27 63.555... 864*2/27 64 us    
Active period 720/27 53.3 720/27 53.3 us    
Tfield 262*858*2/27 16.6515 312*864*2/27 19.688 ms   non-interlaced
Frame rate = 1/Tfield   60.0544...   50.792....    
Tfield 525*858*2/27 33366.6 625*864*2/27 40. ms   interlaced
Frame rate = 1/Tfield   29.970029   25. Hz  

We can see that the timings give exactly 64 us line period and 25 Hz frame rate for PAL,
and exactly the same active pictue time for both PAL and NTSC.

Other interesting points are that 27 MHz and the 4xNTSC carrier have a relationship:

4* Fc * 66 = 945 = 27 * 35

If crystals were available to run at 945 MHz, frequencies could be obtained by divisors:

945 / 66 = 315/22 = 4* Fc
945 / 35 = 27
945 / 27 = 35

For timing purposes, these frequencies have co-incident edges every 66 microseconds:

4* Fc / 945 = (315/22)/945 = 1 / 66 MHz
27 / (27*66) = 27 / 1782 = 1 / 66 MHz
35 / (35*66) = 35 / 2310 = 1 / 66 MHz

Crystals are not commonly available at 27 and 35 MHz, so these frequencies might perhaps be generated by a fractional-N multiplier:

4* Fc * 66 / 35 = 27
4* Fc * 66 / 27 = 35