----------------------------------------------------------------
|Mnem.|Op|NVBDIZC|A#ZBIRX@|~|Description           |Notes      |
|-----+--+-------+--------+-+----------------------+-----------|
|ADC s|6D|**---**| XxX  X |4|Add with Carry        |A=A+s+C   %|
|AND s|2D|*----*-| XxX  X |4|Logical AND           |A=A&s     %|
|ASL d|0E|*----**|  xx    |6|Arithmetic Shift Left |d={C,d,0}<-|
|asla |0a|*----**|x       |2|arithmetic shift left |a="{c,d,0}<-|"
|bcc a|90|-------|     x  |2|branch if carry clear |if c="0(4~)%|"
|bcs a|b0|-------|     x  |2|branch if carry set   |if c="1(4~)%|"
|beq a|f0|-------|     x  |2|branch if equal       |if z="1(4~)%|"
|bit s|2c|**---*-|  **    |4|bit test              |a&s        |
|bmi a|30|-------|     x  |2|branch if minus       |if n="1(4~)%|"
|bne a|d0|-------|     x  |2|branch if not equal   |if z="0(4~)%|"
|bpl a|10|-------|     x  |2|branch if plus        |if n="0(4~)%|"
|brk  |00|--+-1--|    x   |7|break  (-[s]="{pc+2,p})|pc=[fffeh]" |
|bvc a|50|-------|     x  |2|branch if overflow clr|if v="0(4~)%|"
|bvs a|70|-------|     x  |2|branch if overflow set|if v="1(4~)%|"
|clc  |18|------0|    x   |2|clear carry flag      |c="0"        |
|cld  |d8|---0---|    x   |2|clear decimal mode    |d="0"        |
|cli  |58|----0--|    x   |2|clear int. disable    |i="0"        |
|clv  |b8|-0-----|    x   |2|clear overflow flag   |v="0"        |
|cmp s|cd|*----**| xxx  x |4|compare               |a-s        |
|cpx s|ec|*----**| x**    |4|compare index register|x-s        |
|cpy s|cc|*----**| x**    |4|compare index register|y-s        |
|dec d|ce|*----*-|  xx    |6|decrement             |d="d-1"      |
|dex  |ca|*----*-|    x   |2|decrement index reg.  |x="x-1"      |
|dey  |88|*----*-|    x   |2|decrement index reg.  |y="y-1"      |
|eor s|4d|*----*-| xxx  x |4|logical exclusive or  |a="axs"     %|
|inc d|ee|*----*-|  xx    |6|increment             |d="d+1"      |
|inx  |e8|*----*-|    x   |2|increment index reg.  |x="x+1"      |
|iny  |c8|*----*-|    x   |2|increment index reg.  |y="y+1"      |
|jmp s|4c|-------|   *   x|3|jump                  |          !|
|jsr s|20|-------|   *    |6|jump to subroutine    |-[s]="pc+2,!|"
|lda s|ad|*----*-| xxx  x |4|load accumulator      |a="s"       %|
|ldx s|ae|*----*-| xyy    |4|load index register   |x="s"       %|
|ldy s|ac|*----*-| xxx    |4|load index register   |y="s"       %|
|lsr d|4e|0----**|  xx    |6|logical shift right   |d="-">{0,d,C}|
|LSRA |4A|0----**|X       |2|Logical Shift Right   |A=->{0,A,C}|
|NOP  |EA|-------|    X   |2|No Operation          |           |
|ORA s|0D|*----*-| XxX  X |4|Logical Inclusive OR  |A=Avs      |
|PHA  |48|-------|    X   |3|Push Accumulator      |-[S]=A     |
|PHP  |08|-------|    X   |3|Push status register  |-[S]=P     |
|PLA  |68|-------|    X   |4|Pull Accumulator      |A=[S]+     |
|PLP  |28|*******|    X   |4|Pull Status Register  |P=[S]+     |
|ROL d|2E|*----**|  xx    |6|Rotate left           |d={C,d}<-  |
|rola |2a|*----**|x       |2|rotate left acc.      |a="{c,a}<-"  |
|ror d|6e|*----**|  xx    |6|rotate right          |d="-">{C,d}  |
|RORA |6A|*----**|X       |2|Rotate Right Acc.     |A=->{C,A}  |
|RTI  |40|*******|    X   |6|Return from Interrupt |{PC,P}=[S]+|
|RTS  |60|-------|    X   |6|Return from Subroutine|PC={[S]+}+1|
|SBC s|ED|*----**| XxX  X |4|Subtract with Carry   |A=A-s-C   %|
|SEC  |38|------1|    X   |2|Set Carry flag        |C=1        |
|SED  |F8|---1---|    X   |2|Set Decimal mode      |D=1        |
|SEI  |78|----1--|    X   |2|Set Interrupt disable |I=1        |
|STA d|8D|-------|  xX  X |4|Store Accumulator     |d=A        |
|STX d|8E|-------|  y*    |4|Store index register  |d=X        |
|STY d|8C|-------|  x*    |4|Store index register  |d=Y        |
|TAX  |AA|*----*-|    X   |2|Transfer Accumulator  |X=A        |
|TAY  |A8|*----*-|    X   |2|Transfer Accumulator  |Y=A        |
|TSX  |BA|*----*-|    X   |2|Transfer Stack pointer|X=S        |
|TXA  |8A|*----*-|    X   |2|Transfer index reg.   |A=X        |
|TXS  |9A|-------|    X   |2|Transfer index reg.   |S=X        |
|TYA  |98|*----*-|    X   |2|Transfer index reg.   |A=Y        |
|-----+--+-------+--------+-+----------------------------------|
|     |XX|       |        |X|Hexadecimal opcode/no. of cycles  |
|--------+-------+--------+-+----------------------------------|
|        |-      |        | |Flag unaffected                   |
|        |*      |        | |Flag affected                     |
|        |0      |        | |Flag reset                        |
|        |1      |        | |Flag set                          |
|        |+      |        | |Flag set on stack                 |
|--------+-------+--------+-+----------------------------------|
| N      |N      |        | |Negative status (Bit 7)           |
| V      | V     |        | |Overflow status (Bit 6)           |
| B      |  B    |        | |Break command indicator (Bit 4)   |
| D      |   D   |        | |Decimal mode control (Bit 3)      |
| I      |    I  |        | |Interrupt disable control (Bit 2) |
| Z      |     Z |        | |Zero status (Bit 1)               |
| C      |      C|        | |Carry status (Bit 0)              |
----------------------------------------------------------------
----------------------------------------------------------------
|Mnemonic        |A#ZBIRX@|Description             |Opcode| ~s |
|----------------+--------+------------------------+------+----|
|                |X       |All mode(s) valid       |      |    |
|                |*       |Non-indexed mode valid  |      |    |
|                |x       |X/non-indexed mode valid|      |    |
|                |y       |Y/non-indexed mode valid|      |    |
|----------------+--------+------------------------+------+----|
|                |        |Add XXH to opcode       | +XXH |    |
|                |        |Subtract XXH from opcode| -XXH |    |
|                |        |Add X to no. of cycles  |      | +X |
|                |        |Subtract X from cycles  |      | -X |
|----------------+--------+------------------------+------+----|
| A              |A       |Accumulator             |      |    |
| #n             | #      |Immediate               | -04H | -2 |
| nn            |   *    |Absolute                | +00H | +0 |
| nn             |   *    |Absolute (EXTEND mode)  | +00H | +0 |
| nn,X           |   x    |Absolute indexed (X)    | +10H | +0 |
| nn,Y           |   y    |Absolute indexed (Y)    | +0CH | +0 |
| LDX nn,Y       |   y    | ditto                  | +10H | +0 |
|                |    I   |Implicit                |      |    |
| a              |     R  |Relative(PC=PC+1+offset)|      | +2 |
| [nn,X]         |      x |Indexed indirect (X)    | -0CH | +2 |
| [nn],Y         |      y |Indirect indexed (Y)    | +04H | +1 |
| [nn]           |       @|Absolute indirect       | +20H | +2 |
|-------------------------+------------------------------------|
|BYTE     n(,...)         |Byte(s) (8-bit)                     |
|BYTE     'string'(,...)  |Byte text string(s)                 |
|DIRECT                   |Zero page addressing mode           |
|EXTEND                   |Absolute addressing mode            |
|RMB      nn(,...)        |Reserve Memory Bytes                |
|WORD     nn(,...)        |Word(s) (16-bit)                    |
|-------------------------+------------------------------------|
| A                       |Accumulator (8-bit)                 |
| P                       |Processor status register (8-bit)   |
| PC                      |Program Counter (16-bit)            |
| S                       |Stack pointer (9-bit, MSB=1)        |
| X                       |Index register X (8-bit)            |
| Y                       |Index register Y (8-bit)            |
|-------------------------+------------------------------------|
| a                       |Relative address (-128 to +127)     |
| d                       |Destination                         |
| n                       |8-bit expression (0 to 255)         |
| nn                      |16-bit expression (0 to 65535)      |
| s                       |Source                              |
| string                  |String of ASCII characters          |
|-------------------------+------------------------------------|
| +                       |Arithmetic addition                 |
| -                       |Arithmetic subtraction              |
| *                       |Arithmetic multiplication           |
| /                       |Arithmetic division                 |
| &                       |Logical AND                         |
| ~                       |Logical NOT                         |
| v                       |Logical inclusive OR                |
| x                       |Logical exclusive OR                |
| <-                      |rotate left                         |
| ->                      |Rotate right                        |
| [ ]                     |Indirect addressing                 |
| [ ]+                    |Indirect addressing, auto-increment |
| -[ ]                    |Auto-decrement, indirect addressing |
| { }                     |Combination of operands             |
| $                       |Program counter content             |
| %                       |~s = ~s+1 if crossing page boundary |
| !                       |PC = effective address of source    |
| -->                     |Input pin                           |
| <--                     |output pin                          |
| <-->                    |Input/output pin                    |
|-------------------------+------------------------------------|
|0000H to 00FFH           |Page 0 (see zero page addressing)   |
|0100H to 01FFH           |Page 1 (stack area, 01FFH = start)  |
|XX00H to XXFFH           |Page n (where n=XXH)                |
|FFFAH to FFFBH           |Non maskable interrupt (NMI) vector |
|FFFCH to FFFDH           |Reset (RES) vector                  |
|FFFEH to FFFFH           |Interrupt Request (IRQ) vector      |
|FFFEH to FFFFH           |Interrupt Request (IRQ) vector      |
|FFFEH to FFFFH           |Break command vector (see BRK)      |
|Issue          1.5                Copyright (C) J.P.Bowen 1985|
|               Oxford University Computing Laboratory         |
----------------------------------------------------------------