Approximate VHDL entity only!

entity VIA_6522 is	-- 
port(
	n_rst:	in	std_logic;	-- Reset
	n_wr:	in	std_logic;	-- Read / Not Write
	ph2:	in	std_logic;	-- CPU clock phase 2
	cs1:	in	std_logic;
	n_cs2:	in	std_logic;
	rs:	in	std_logic_vector(3 downto 0);
	d:	inout	std_logic_vector(7 downto 0);
	pa:	inout	std_logic_vector(7 downto 0);	-- Port A
	ca:	inout	std_logic_vector(2 downto 1);	-- Port CA
	pb:	inout	std_logic_vector(7 downto 0);	-- Port B 
	cb:	inout	std_logic_vector(2 downto 1);	-- Port CB
	);
end entity VIA_6522;