The 6522 Versatile Interface Adapter chip

The 6522 VIA chip can be added to the Atom to provide printer or other parallel I/O. It is a very clever chip which can handle many parallel or serial I/O functions. A full description would occupy many pages and be beyond the scope of this book, but the following paragraphs show the simpler functions satisfactory for most applications.

The VIA has two 8-bit bi-directional I/O ports connected to the I/O lines PA0-7 and PB0-7, two 16-bit counter/timers, an 8-bit serial shift register, and some control circuitry associated with the four lines CA1-2, CB1-2. It appears as 16 registers;

Each bit of ports A and B can be made an input by writing '0' to the corresponding bit of the direction register ('1' = output). Once the bit direction has been programmed, the port registers (B800 and B801) may be read or written as any other memory location. reading output bits will just return the value last written to them. Writing to an input bit does nothing.

PA0-7 and PB0-7 presents one TTL load as an input, and can drive one TTL load as an output. PB0-7 outputs can source 3mA at 1V5 when high, useful for driving NPN transistors.

Bits 0 and 1 of B80B should normally be zero. Setting either to 1 invokes a complex latching arrangement for data input to ports A and B.

The 16-bit timer 1 counts down at 1MHz, and has two associated 8-bit latches. Writing to B804 latches the low count data byte. Reading B804 returns the low 8 bits of the counter. Reading B805 returns the high 8 bits of the counter. You can read and write the two latches at B806 and B807 without affecting the counter.

If bit 6 of the auxiliary control register (B80B) is '0', the counter will decrement continually at 1MHz, and set the interrupt flag the first time it reaches zero. This is the 'one-shot' timing mode. If B80B bit 6 is '1', the counter will decrement at 1MHz, but will reload from the two latches as well as setting the T1 interrupt flag. This is the 'free-running' mode, and PB7 toggles each time the counter reaches zero.

The 16-bit timer 2 is similar but there are some differences. Writing to B808 stores the data in an 8-bit latch, reading B808 returns the low byte of the counter. Writing to B809 directly loads the high byte of the counter then loads the low-byte of the counter with the data from the latch. Reading B809 returns the high 8 bits of the counter.

Timer 2 can be clocked from either of two sources; if bit 5 of B808 is '0', the counter decrements at 1MHz. If bit 5 is '1', the counter is decremented by each falling edge applied to PB6. In all cases the timer operates in the 'one-shot' mode; the counter is started by writing to B809, and on reaching zero the T2 interrupt flag becomes '1' and the counter continues to decrement.

The 8-bit shift register uses CB2 for serial input or output, and CB1 for clock pulse input or output. Its operation is controlled by B80B bits 2, 3 and 4.

In the timer 2' modes, only the low byte of the timer is used. In all cases data are clocked on the rising edge of the internal or external clock pulse on CB1, and - except for the repetitive' mode - shifting (and clock pulses supplied to CB1) stops after 8 bits have been shifted in or out. The shift register interrupt flag then becomes '1'. This flag is made '0' by reading or writing of the shift register.

The function of the four control lines are (except when CB1 or CB2 are used by timer 2 or the shift register) determined by the Peripheral Control register at B80C. Most modes are intended for complex interrupt/handshake operations. CA2 and CB2 can be used as simple I/O lines via bits 0 and 5 respectively of B80C if all other bits of B80C are set to '1'.

The interrupt flag register (B80D) has 7 bits which are set to '1' by particular events inside the VIA chip, and set to '0' by reading or writing particular registers.

The Interrupt enable register at B80E has 6 interrupt enable bits corresponding to the six bits in the Interrupt flag register. Most applications will not use interrupts, so 00 should be written to B80E. This will not affect the setting of bits in B80D, but will prevent them interrupting the processor.